The present invention relates to high-performance metal oxide semiconductor field effect transistors (MOSFETs) for digital or analog applications, and more particularly to MOSFETs utilizing carrier mobility enhancement from substrate surface orientation.
In present semiconductor technology, complementary metal oxide semiconductor (CMOS) devices, such as nFETs (i.e., n-channel MOSFETs) or pFETs (i.e., p-channel MOSFETs), are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today""s semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2xc3x97-4xc3x97 lower than the corresponding electron hole mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area.
On the other hand, hole mobilities on (110) Si are 2xc3x97 higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
As can be deduced from the above, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
In view of the above, there is a need for providing integrated semiconductor devices that are formed upon a substrate having different crystal orientations that provide optimal performance for a specific device. A need also exists to provide a method to form such an integrated semiconductor device in which both the nFETs and the pFETs are formed on a silicon-on-insulator substrate having different crystallographic orientations in which the semiconducting layers that the devices are built upon are substantially coplanar and have substantially the same thickness.
One object of the present invention is to provide a method of fabricating integrated semiconductor devices such that different types of CMOS devices are formed upon a specific crystal orientation of a silicon-on-insulator (SOI) substrate that enhances the performance of each device.
Another object of the present invention is to provide a method of fabricating integrated semiconductor devices such that the pFETs are located on a (110) crystallographic plane, while the nFETs are located on a (100) crystallographic plane of the same SOI substrate.
A further object of the present invention is to provide a method of integrating SOI technology with CMOS technology using simple and easy processing steps.
A still further object of the present invention is to provide a method of forming an integrated semiconductor structure in which both CMOS devices, i.e., pFETs and nFETs, are SOI like.
A yet further object of the present invention is to provide a method of forming an integrated semiconductor structure comprising an SOI substrate having different crystal orientations in which the semiconducting layers that the devices are built upon are substantially coplanar and have substantially the same thickness.
These and other objects and advantages are achieved in the present invention by utilizing a method that includes wafer bonding, etching, regrowth of a semiconductor layer in the etched area and ion implanting and annealing, e.g., SIMOX (separation by implanted oxygen). Specifically, the method of the present invention first includes providing an SOI substrate that includes at least a top semiconductor layer and a bottom semiconductor layer of different crystallographic orientations. The SOI substrate is provided by bonding two different semiconductor wafers together. After bonding, an opening that exposes a surface of the bottom semiconductor layer of the SOI substrate is formed utilizing a selective etching process.
Next, a semiconductor material having the same crystallographic orientation as that of the bottom semiconductor layer is epitaxially grown in the opening on the exposed surface of the bottom semiconductor layer. Spacers may be formed on the exposed sidewalls of the opening prior to forming the semiconductor material. A SIMOX like process (including ion implantation of oxygen or nitrogen and annealing) is used to form a buried insulating region within the semiconductor material.
Following the implanting and annealing, a planarization step is employed to provide a structure in which the semiconductor material having the second crystallographic orientation is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer. At least one nFET and at least one pFET may then be formed on either the top semiconductor layer or the semiconductor material depending on the surface orientation of that layer. Both CMOS devices, i.e., the nFET and the pFET are SOI like devices since that are formed in a SOI layer, i.e., the top semiconductor layer or the regrown semiconductor material, that is separated from the bottom semiconductor layer by a buried insulating layer.